3092641 Principal Engineer – RISC-V CPU Sub-System Architecture – Hod Hasharon / Haifa

Key Responsibilities

• Own CPU sub-system architecture including core integration, cache hierarchy, memory, and interconnect
• Define architecture specifications and integration guidelines
• Lead integration into complex SoCs and align across HW/SW teams
• Drive PPA tradeoffs %28performance, power, area%29
• Diagnose system-level issues across architecture, RTL, DV, and firmware
• Act as technical focal point across global teams
• Lead architecture and design reviews
• Mentor engineers across architecture and VLSI teams
• Define and integrate NoC architecture including traffic, QoS, and scalability
• Define and work with high-performance bus protocols including AXI and CHI

Minimum Qualifications

• B.Sc. in Electrical Engineering / Computer Engineering / Computer Science
• 10+ years of experience
• Strong background in CPU/SoC architecture
• Deep knowledge of cache, memory, and interconnect systems
• Experience with RISC-V or similar architectures
• Strong RTL development experience
• Experience with NoC architecture and on-chip interconnects
• Experience with AXI / CHI protocols
• strong problem-solving and communication skills