- מיקום
- כל הארץ
- היקף משרה
- משרה מלאה
- תפקיד
- מהנדס/ת חומרה ואלקטרוניקה
תיאור המשרה
Key responsibilities
- Define DFT architecture, strategy, and implementation methodology.
- Lead scan insertion, compression, ATPG, MBIST, and JTAG implementation.
- Own DFT verification, coverage analysis, debugging, and signoff.
- Address timing, power, and physical-design considerations related to DFT.
- Support silicon bring-up, diagnosis, and production-test readiness.
- Build and improve automated, scalable DFT flows.
- Collaborate with design, backend, STA, verification, and validation teams.
Requirements:
- 7+ years of hands-on DFT experience in complex ASIC/SoC designs.
- Proven ownership of DFT through at least one full tapeout cycle.
- Strong experience with Scan/ATPG, MBIST, JTAG, insertion, verification, and coverage closure.
- Experience with industry-standard DFT tools, such as Siemens Tessent or Synopsys TestMAX/DFTMAX.
- Solid understanding of STA, physical-design constraints, clocking, reset, power, and DFT-related timing considerations.
- Ability to independently define methodology and drive cross-functional technical decisions.
- Strong communication and problem-solving skills.
Advantages
- Experience with hierarchical DFT, low-power designs, advanced compression, diagnosis, or yield improvement.
- Experience with Analog/Mixed-Signal DFT, including test architecture and testability of analog/mixed-signal blocks.
- Familiarity with analog test interfaces, boundary scan extensions, ADC/DAC testing, PLL/clocking test, or other mixed-signal test methodologies.
- Post-silicon bring-up and production-test experience.
- Experience establishing DFT flows from the ground up.
