Experienced Back-End Engineer

Description

We’re a leading ASIC design and manufacturing company, delivering complete ASIC and COT solutions and turnkey manufacturing to fabless companies and OEMs building advanced SoCs. Our engineers work across the full chip lifecycle: architecture, RTL-to-GDSII implementation, analog/mixed-signal design, and productization through silicon, package, and test. As an authorized TSMC Value Chain Alliance (VCA) member, we work on process nodes from 180nm down to 2nm. With 350+ tape-outs since 1986, you’ll join a team with deep expertise and the chance to work on cutting-edge silicon.

We are hiring an Experienced Back-End (Physical Design) Engineer in Moshav Bnei Dror to take customer SoC blocks from netlist to GDSII: floorplan, place & route, clock tree synthesis, timing closure, power grid analysis and physical verification sign-off.

Requirements

Must-Have Requirements:

• BSc in Electrical Engineering from a recognized university.
• Minimum 6 years of back-end / physical design experience — must.
• Floorplanning and Place & Route.
• Timing closure and debug, Static Timing Analysis (STA).
• Clock Tree Synthesis (CTS).
• Power grid analysis (IR drop / EM).
• LVS / DRC debug (physical verification).

Nice to Have:

• DFT experience.
• Synopsys IC Compiler (ICC / ICC2) experience.