Senior SoC Design Engineer %28AI Inference Systems – ASIC/CPU/GPU%29

Role Summary

We are seeking a highly skilled, hands-on Senior
SoC Design Engineer to drive the integration, front-end architecture, and
delivery of our custom AI inference System-on-Chip %28SoC%29. In this role, you
will be a core technical contributor owning the integration of complex IP
blocks, high-speed networking, advanced memory subsystems, and cutting-edge
multi-die/multi-chip interconnects. 

Your mandate will focus on weaving together our
custom high-throughput AI acceleration blocks with industry-standard
subsystems, advanced network-on-chip %28NoC%29 fabrics, and modern packaging
technologies. Working in a tight-knit startup environment, you will collaborate
closely with software compiler teams, silicon architects, physical design
groups, and verification teams to deliver highly optimized, production-ready
multi-die silicon for next-generation data center environments. 

Key Responsibilities  

• SoC Integration & RTL Design: Own the top-level and subsystem-level SoC integration, defining the chiplayout fabric and writing clean, synthesizable SystemVerilog code fortop-level control, routing, and fabric logic. 
• Multi-Die &Multi-Chip Connectivity: Design and integrate low-latency, high-bandwidth streaming configurations:  
• Die-to-Die%28D2D%29:Implementation and integration of industry-standard UCIe %28Universal Chiplet Interconnect Express%29 or Bunch of Wires %28BoW%29 protocols across multi-die systems. 
• Chip-to-Chip %28C2C%29: Integration of proprietary or open high-speed coherent interconnects enabling scalable, low-latency scale-out compute nodes.  
• Advanced Fabric & Protocol Configuration: Integrate and optimize complex Network-on-Chip %28NoC%29 architectures and advanced data center peripherals, including ultra-high-speed networking %28100G / 400G / 800G / 1.6T Ethernet%29, bleeding-edge host interfaces %28PCIe Gen5 / Gen6 / Gen7%29, and modern memory sub-systems %28DDR, LPDDR6, LPDDR6x, HBM%29. 
• Advanced Packaging Collaboration: Work with silicon architects and physical design teams to define hardware partitioning supporting advanced packaging paradigms %28e.g., 2.5D/3D IC, chiplets, interposers, CoWoS%29 and ensure seamless protocol-to-physical layer interoperation. 
• Front-End Quality & Delivery:M Drive block- and chip-level front-end quality checks, including synthesis, linting, clock domain crossing %28CDC%29 analysis, reset domain crossing %28RDC%29, and static timing analysis %28STA%29 constraints to achieve optimal Power, Performance, and Area %28PPA%29. 
• Cross-Functional Alignment: Coordinate closely with Design Verification %28DV%29 teams to triage
  simulation anomalies and close coverage metrics, while collaborating with Physical Design %28PD%29 to resolve layout and timing closure bottlenecks. 

Key Requirements & Qualifications

• Education &Experience:Bachelor’s or Master’s degree in Electrical/Computer Engineering or arelated field, with 5+ years of hands-on ASIC/SoC design, integration, andfront-end development experience. 
• Expert SoC Integration: Proven track record of delivering complex, multi-million gate SoCs with multiple successfultape-outs, displaying deep expertise in SystemVerilog/Verilog and automated chip assembly flows. 
• Chiplet, Die-to-Die, and
  Chip-to-Chip Protocols: Direct engineering experience integrating high-density
  interconnect technologies, specifically UCIe, with an understanding
  of protocol, adapter, and physical layer streaming. 
• Modern Peripherals &
  High-Speed IO:
  Hands-on experience integrating modern ultra-high-bandwidth connectivity
  standards, including:  
• Networking
  & Protocols:
  Next-generation high-throughput 100G, 400G, 800G, and 1.6T Ethernet
  configurations or custom low-latency cluster interconnects. 
• Host
  & System IO:
  PCIe Gen5/Gen6 %28or early Gen7 exploration%29, CXL, and standard
  connectivity peripherals like USB. 
• Memory
  Subsystems:
  Deep familiarity with modern memory standards, notably DDR, LPDDR6/6x, or
  HBM.  
• Advanced Packaging
  Exposure:
  Engineering familiarity with advanced silicon packaging architectures %282.5D,
  3D IC, or similar chiplet topologies%29 and the design requirements
  associated with multi-die integration. 
• Startup Agility: Exceptional capability
  to thrive in a fast-paced, high-ambiguity startup environment. A pragmatic
  engineer who knows how to deliver robust silicon architecture within
  aggressive development timelines. 
• EDA Tool Ecosystem: Deep familiarity with
  industry-standard EDA front-end tool suites %28Synopsys, Cadence, or
  Siemens%29 for simulation, synthesis, and timing constraints management.