ASIC Design Verification Senior Engineer

ASIC Design Verification Senior Engineer 

General Summary

As a Senior RTL Verification Engineer, you will lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC‑V Application Processor. You will work closely with architecture, design, modeling, software, validation, and implementation teams to ensure first-pass silicon success while meeting aggressive performance, power, and area %28PPA%29 targets.

In this role, you will drive verification strategy, methodology, and execution from specification through tape-out, providing technical leadership in the definition of scalable verification environments, coverage closure plans, and debug methodologies. You will be expected to independently own large verification domains, influence design and architecture decisions, and mentor junior engineers.

The ideal candidate has extensive experience in CPU or SoC verification, with strong expertise in one or more of the following areas: RISC‑V architecture, CPU microarchitecture, MMU, memory hierarchy, cache coherence, interconnects, and micro-controller verification.

Responsibilities

Lead verification efforts for complex CPU and SoC subsystems from architecture definition through tape-out.

Define comprehensive verification strategies, test plans, coverage models, and closure criteria.

Architect, develop, and maintain advanced UVM-based verification environments and reusable verification components.

Drive verification execution, including stimulus development, functional coverage closure, assertions, regressions, and debug.

Collaborate closely with architecture and design teams to review specifications, identify ambiguities, and ensure verifiability.

Develop constrained-random, directed, and scenario-based tests to validate functional correctness and corner cases.

Drive root-cause analysis and resolution of complex design and verification issues.

Define and implement verification methodologies that improve scalability, quality, and productivity across the project.

Work with software, modeling, performance, and validation teams to develop system-level verification solutions.

Analyze verification metrics and risks, proactively driving closure plans to achieve project milestones.

Mentor junior verification engineers and contribute to the technical growth of the team.

Contribute to DV methodology discussions and influence verification best practices across the organization.

Required Skills and Experience

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or related field.

5+ years of experience in RTL ASIC verification with demonstrated ownership of complex verification projects.

Strong knowledge of microprocessor architecture and verification methodologies.

Experience with one or more of the following:

CPU microarchitecture

RISC‑V architecture

MMU and virtual memory systems

Cache and memory subsystems

Coherency protocols

Interconnect and SoC architecture

Strong expertise in SystemVerilog and UVM.

Experience developing scalable constrained-random verification environments.

Experience with assertions and assertion-based verification %28SVA%29.

Experience with Verilog and RTL debugging.

Strong programming skills in C/C++ and/or DPI-C.

Experience with functional coverage planning, implementation, and closure.

Experience debugging complex hardware and verification issues independently.

Strong communication and collaboration skills with cross-functional engineering teams.

Ability to communicate complex technical concepts clearly in fluent English.