Senior Verification Engineer

Key responsibilities:

• Ownership of blockcluster verification end to end from scratch.

• Lead efforts of test bench architecture, Vplan definition and functional coverage.

• Work closely with the design, architecture, algo teams and other stakeholders.

• Support other team members and mentor less experienced engineers.

Requirements

• 10+ years of experience – a must

• Performed at last 2 or more full block/system verification cycles.

• In depth knowledge in VLSI verification flow, languages and concepts.

• Experience in data path or data protocols, specifically Ethernet – preferred

• Verification using one of the known methodologies %28eRM, UVM, OVM%29.

Responsibilities

• Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.

• Build verification environments using SystemVerilog and UVM.

• Identify and write all types of coverage measures for corner-cases.

• Debug the functionality with design engineers.

• Perform coverage collection and follow the metrices to close the full functionality.