SoC Design Engineer %28AI Inference Systems – ASIC/CPU/GPU%29

Description:

We are seeking a talented, hands-on SoC Design Engineer to contribute to the integration, front-end design, and delivery of our custom AI inference System-on-Chip %28SoC%29. In this role, you will work alongside senior architects and engineers to integrate complex IP blocks, high-speed networking, advanced memory subsystems, and cutting-edge multi-die/multi-chip interconnects.

Your mandate will focus on implementing and weaving together our custom high-throughput AI acceleration blocks with industry-standard subsystems, advanced network-on-chip %28NoC%29 fabrics, and modern packaging technologies. Working in a tight-knit startup environment, you will collaborate closely with software compiler teams, silicon architects, physical design groups, and verification teams to deliver highly optimized, production-ready multi-die silicon for next-generation data center environments.

Key Responsibilities:

• SoC Integration & RTL Design: Participate in top-level and subsystem-level SoC integration, implementing the chip layout fabric and writing clean, synthesizable SystemVerilog code for control, routing, and fabric logic.
• Multi-Die & Multi-Chip Connectivity: Implement and integrate low-latency, high-bandwidth streaming configurations under the guidance of senior technical leads:
• Die-to-Die %28D2D%29: Logic design and integration of industry-standard UCIe %28Universal Chiplet Interconnect Express%29 or Bunch of Wires %28BoW%29 protocols across multi-die systems.
• Chip-to-Chip %28C2C%29: Integration of proprietary or open high-speed coherent interconnects enabling scalable, low-latency scale-out compute nodes.
• Advanced Fabric & Protocol Configuration: Configure and optimize complex Network-on-Chip %28NoC%29 architectures and advanced data center peripherals, including ultra-high-speed networking %28100G / 400G / 800G / 1.6T Ethernet%29, bleeding-edge host interfaces %28PCIe Gen5 / Gen6 / Gen7%29, and modern memory sub-systems %28DDR, LPDDR6, LPDDR6x, HBM%29.
• Advanced Packaging Collaboration: Work with cross-functional teams to implement hardware partitioning supporting advanced packaging paradigms %28e.g., 2.5D/3D IC, chiplets, interposers, CoWoS%29 and ensure seamless protocol-to-physical layer interoperation.
• Front-End Quality & Delivery: Run block- and chip-level front-end quality checks, including synthesis, linting, clock domain crossing %28CDC%29 analysis, reset domain crossing %28RDC%29, and static timing analysis %28STA%29 constraints to achieve optimal Power, Performance, and Area %28PPA%29.
• Cross-Functional Alignment: Coordinate closely with Design Verification %28DV%29 teams to debug simulation anomalies and close coverage metrics, while collaborating with Physical Design %28PD%29 to resolve layout and timing closure bottlenecks.

  Requirements:

• Education & Experience: Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field, with 2–5 years of hands-on ASIC/SoC design, integration, and front-end development experience.
• Solid SoC Integration: Proven experience delivering digital logic design and integration for complex SoCs, possessing strong proficiency in SystemVerilog/Verilog and automated chip assembly flows.
• Chiplet & Interface Exposure: Practical engineering familiarity with high-density interconnect technologies like UCIe or similar die-to-die streaming protocols.
• Modern Peripherals & High-Speed IO: Hands-on familiarity or direct experience configuring modern ultra-high-bandwidth connectivity standards, including:
• Networking & Protocols: High-throughput 100G, 400G, 800G, or 1.6T Ethernet configurations.
• Host & System IO: PCIe Gen5/Gen6 %28or early Gen7 exploration%29, CXL, and standard connectivity peripherals like USB.
• Memory Subsystems: Understanding of modern memory architectures, notably DDR, LPDDR6/6x, or HBM.
• Advanced Packaging Awareness: Structural familiarity with advanced silicon packaging concepts %282.5D, 3D IC, or similar chiplet topologies%29 and how they impact front-end constraints.
• Startup Agility: Exceptional capability to thrive in a fast-paced, high-ambiguity startup environment. A proactive engineer who is eager to learn and resolve complex integration dependencies.
• EDA Tool Ecosystem: Hands-on experience with industry-standard EDA front-end tool suites %28Synopsys, Cadence, or Siemens%29 for simulation, synthesis, and timing constraints verification.