VLSI Design Engineer

Job Description: VLSI Design Engineer %28AI Inference Hardware – ASIC/CPU/GPU%29

Company Overview

We are an ambitious, fast-growing, early-stage startup pioneering the next generation of AI acceleration computing. We are building revolutionary silicon architectures specifically optimized to run massive deep learning workloads in modern data centers. If you want to design high-performance microarchitectures from the ground up and directly shape the future of data center AI compute, this is your playground.

Role Summary

We are seeking a talented, hands-on VLSI Design Engineer to contribute to the microarchitecture, logic design, and block-level implementation of our custom AI inference acceleration hardware. In this role, you will work alongside senior architects and engineers to design and verify high-throughput compute engines, advanced memory subsystems, and specialized data path architectures for our ASIC/CPU/GPU platform.

This is an execution-focused role where you will directly impact our silicon performance, transforming advanced machine learning workload profiles into clean, optimized RTL. Working in a tight-knit startup environment, you will collaborate across software, system, and design verification teams to ensure first-time-right silicon for next-generation data center deployments.

Key Responsibilities

• Microarchitecture & RTL Design: Develop microarchitecture specifications and write clean, synthesizable, high-performance RTL %28SystemVerilog/Verilog%29 for custom AI inference accelerator blocks, processing units, and high-bandwidth local interconnects.
• Hardware-Software Co-Design Support: Work alongside software compiler and systems engineering teams to profile data center workload bottlenecks, using simulation data to refine block-level microarchitecture for maximum compute utilization.
• IP Block Integration: Implement block-level logic design for specialized compute components %28e.g., matrix multiplication blocks, tensor pipelines, or specialized vector execution engines%29 and integrate them into larger processor complexes.
• Front-End Quality & Delivery: Run block-level front-end quality checks using industry-standard EDA tools, including synthesis, linting, clock domain crossing %28CDC%29 analysis, and reset domain crossing %28RDC%29.
• Verification & Debugging: Partner closely with the Design Verification %28DV%29 team to review test plans, debug simulation failures/waveforms, and isolate logic bugs in the design blocks.

Key Requirements & Qualifications

• Education & Experience: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 2–5 years of hands-on digital logic design and front-end ASIC/IC development experience.
• Proficient RTL Development: Solid proficiency in SystemVerilog or Verilog for complex, high-performance digital circuit design.
• Foundational AI Hardware Knowledge: Strong understanding of processing architectures used to accelerate AI inference %28e.g., pipelined math engines, multi-dimensional execution structures, and localized scratchpad/caching memories%29.
• Data Path Implementation: Direct experience designing data paths, pipelined control structures, execution multiplexers, or custom DMA blocks.
• Startup Agility & Collaboration: Exceptional capability to thrive in a fast-paced, high-ambiguity startup environment. A proactive learner who takes ownership of tasks and works well across different disciplines.
• EDA Tool Ecosystem: Hands-on experience with industry-standard EDA frontend tool suites %28Synopsys, Cadence, or Siemens%29 for synthesis, linting, and timing constraints management.