Junior VLSI/Verification Engineer

Role Summary

We are seeking a motivated, fast-learning Junior Design Verification %28DV%29 Engineer to support the validation of our custom AI inference hardware platform. In this role, you will work alongside senior verification architects and engineers to write tests, debug logic, and expand testbenches from the block level up to top-level multi-die SoCs.

This is a hands-on technical role where you will quickly gain exposure to modern pre-silicon validation environments. You will learn to use cutting-edge verification methodologies to test high-throughput AI acceleration blocks, advanced chiplet technologies, and bleeding-edge data center peripherals. Working in an agile startup environment, you will collaborate with RTL designers and systems engineers to catch critical bugs and help drive our silicon to a flawless tape-out.

Key Responsibilities

• Testbench Support & Maintenance: Help maintain and build block-level verification environments using UVM %28Universal Verification Methodology%29 and SystemVerilog under the guidance of senior technical mentors.
• Test Case Implementation: Write and run constrained-random test cases, customize sequences, and help add functional coverage to ensure thorough validation of design specifications.
• Modern Protocol Exposure: Learn to implement verification checks for advanced, high-speed data center interfaces under direct mentorship, including:
• Multi-Die / Chiplet: UCIe %28Universal Chiplet Interconnect Express%29 or Bunch of Wires %28BoW%29 architectures.
• Networking & Peripherals: High-throughput network fabrics %28100G / 400G / 800G / 1.6T Ethernet%29 and host interfaces %28PCIe Gen5 / Gen6 / Gen7%29.
• Memory Subsystems: Modern memory spaces including DDR, LPDDR6, LPDDR6x, and HBM.
• Debug & Waveform Analysis: Review regression failures, analyze simulation waveforms %28using tools like Verdi%29, and work closely with RTL design engineers to narrow down and fix functional bugs.
• Scripting & Workflow Automation: Write and modify scripts %28Python, Tcl, or Bash%29 to automate regression scheduling, parse log files, and collect coverage metrics efficiently.

Key Requirements & Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a highly related field.
• Experience Level: 0–2 years of digital circuit validation or design experience %28relevant university projects, lab work, or hardware internships are highly valued%29.
• Core Technical Skills: Strong foundational knowledge of digital logic design, computer architecture, and hardware verification concepts %28SystemVerilog/Verilog, OOP principles%29.
• Familiarity with UVM: Classroom, lab, or internship exposure to UVM concepts %28such as drivers, monitors, agents, and scoreboards%29 is a major plus.
• Scripting Mindset: Basic scripting capabilities %28Python, Tcl, or Bash%29 to handle large log files and automate daily design tasks.
• Eagerness to Learn: A proactive mindset with a strong desire to master complex data center protocols and advanced verification methodologies.
• Startup Adaptability: Excellent communication skills and a highly collaborative mindset, comfortable navigating a fast-paced, evolving startup environment. 

Role Summary

We are seeking a motivated, fast-learning Junior VLSI Engineer to support the microarchitecture, logic design, and block-level implementation of our custom AI inference acceleration hardware. In this role, you will work alongside senior engineers to design and verify high-throughput compute engines, memory subsystems, and data path architectures for our ASIC platform.

This is a hands-on technical role where you will quickly gain exposure to the entire front-end ASIC development lifecycle. You will write RTL, run simulations, and collaborate with software and verification teams to help ensure our silicon delivers maximum performance for modern LLM and generative AI workloads.

Key Responsibilities

• RTL Development: Write, modify, and maintain synthesizable, high-performance block-level RTL %28SystemVerilog/Verilog%29 under the guidance of senior engineering mentors.
• Block-Level Design & Optimization: Work on the logic design of specialized AI compute blocks %28e.g., math pipelines, data buffers, or control logic%29 focusing on optimizing area, speed, and power.
• Front-End Quality Checks: Run industry-standard EDA tools to perform linting, clock domain crossing %28CDC%29 analysis, and basic logic synthesis checks to ensure clean design delivery.
• Simulation & Debugging: Collaborate with the Design Verification %28DV%29 team to simulate design blocks, debug unexpected waveforms, and fix logic bugs in the design.
• Documentation: Create and maintain documentation for microarchitecture specifications, block-level test constraints, and design changes.

Key Requirements & Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a highly related field.
• Experience Level: 0–2 years of ASIC/FPGA design experience %28relevant university projects, lab work, or internships are highly valued%29.
• Core Technical Skills: Strong foundational knowledge of digital logic design, computer architecture, and hardware description languages %28SystemVerilog or Verilog%29.
• Familiarity with Scripting: Basic scripting skills %28Python, Tcl, or Bash%29 to automate daily design tasks and parse tool logs.
• Eagerness to Learn: A proactive mindset with a strong desire to learn about AI hardware execution patterns %28like matrix multiplication, neural networks, or high-bandwidth caching%29.
• Startup Adaptability: Excellent communication skills and a collaborative mindset, comfortable navigating a fast-paced, evolving startup environment.