Verification Engineer

Company Overview

We are an ambitious, fast-growing, early-stage startup pioneering the next generation of AI acceleration computing. We are building revolutionary silicon architectures %28ASIC/CPU/GPU%29 specifically optimized to run massive deep learning workloads in modern data centers. If you want to design and architect cutting-edge verification environments from scratch and ensure the flawless execution of next-generation data center AI compute, this is your playground.

Role Summary

We are seeking a highly skilled, hands-on Senior Design Verification %28DV%29 Engineer to own the verification ecosystem for our custom AI inference platform. In this role, you will be a core technical contributor, architecting and building robust, scalable testbenches from the block level up to top-level multi-die SoCs.

Your mandate will focus on using advanced verification methodologies to thoroughly validate high-throughput AI acceleration blocks, complex Network-on-Chip %28NoC%29 architectures, advanced chiplet technologies, and bleeding-edge data center peripherals. Working in a tight-knit startup environment, you will collaborate closely with silicon architects, SoC integration teams, and physical design groups to ensure first-time-right silicon for complex LLM and generative AI workloads at scale.

Key Responsibilities

• Testbench Architecture & Development: Architect, build, and maintain scalable, modular verification environments at both block and top-level SoC stages using UVM %28Universal Verification Methodology%29 and SystemVerilog.
• Advanced Interface & Protocol Validation: Own the verification strategy and execution for complex multi-die configurations and next-generation high-speed data center peripherals:
• Multi-Die / Chiplet: Validate low-latency, high-bandwidth streaming configurations using UCIe %28Universal Chiplet Interconnect Express%29 or Bunch of Wires %28BoW%29 protocols.
• Networking & Peripherals: Verify ultra-high-speed network fabrics %28100G / 400G / 800G / 1.6T Ethernet%29 and bleeding-edge host interfaces %28PCIe Gen5 / Gen6 / Gen7%29.
• Memory Subsystems: Verify complex interactions with modern memory subsystems including DDR, LPDDR6, LPDDR6x, and HBM.
• Coverage Closure & Bug Hunting: Define comprehensive verification plans, develop functional coverage models, write SystemVerilog Assertions %28SVA%29, and drive constrained-random testing to reach 100% coverage closure.
• Debug & Triage: Lead complex debug activities across simulation environments, analyzing waveforms and working hand-in-hand with RTL designers to isolate and resolve intricate architectural and logic bugs.
• Test Automation & Scripting: Develop and optimize regression scripts and infrastructure automation to ensure efficient utilize of simulation compute licenses in a fast-paced environment.

Key Requirements & Qualifications

• Education & Experience: Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field, with 5+ years of hands-on ASIC/SoC design verification experience.
• Expert UVM/SystemVerilog Proficiency: Deep technical mastery of advanced UVM architectures, constrained-random verification, interface checkers, and VIP %28Verification IP%29 integration.
• Protocol & Packaging Domain Knowledge: Direct experience verifying complex, high-throughput systems including UCIe, ultra-fast Ethernet %28up to 1.6T%29, PCIe Gen5/6, and high-density memory spaces %28LPDDR6/HBM%29.
• AI Compute Cluster Awareness: Strong understanding of verification patterns required for multi-dimensional execution setups %28such as matrix-multiplication blocks, tensor units, and asynchronous data paths%29.
• Startup Agility: Exceptional capability to thrive in a fast-paced, high-ambiguity startup environment. A pragmatic engineer who knows how to balance absolute verification quality with aggressive commercial tape-out timelines.
• EDA Simulation Tools: Expert familiarity with industry-standard EDA simulation and debug suites %28such as Synopsys VCS/Verdi, Cadence Xcelium, or Siemens Questa%29.